can_isr.c

#include <includes.h>

unsigned long can_elapsed_ms = 0;   // CAN module time variable

// CAN error global variables:
volatile unsigned long can_error_1 = 0;
volatile unsigned long can_error_2 = 0;
volatile unsigned long can_error_3 = 0;
volatile unsigned long can_error_4 = 0;

unsigned short can_get_error_1(CAN_FRAME * frame)
{
  frame->payload.w.w1 = can_error_1;
  can_error_1 = 0;     //Reset error
  frame->payload.w.w2 = can_elapsed_ms;
  return 0;
}

unsigned short can_get_error_2(CAN_FRAME * frame)
{
  frame->payload.w.w1 = can_error_2;
  can_error_2 = 0;     //Reset error
  frame->payload.w.w2 = can_elapsed_ms;
  return 0;
}

unsigned short can_get_error_3(CAN_FRAME * frame)
{
  frame->payload.w.w1 = can_error_3;
  can_error_3 = 0;     //Reset error
  frame->payload.w.w2 = can_elapsed_ms;
  return 0;
}

unsigned short can_get_error_4(CAN_FRAME * frame)
{
  frame->payload.w.w1 = can_error_4;
  can_error_4 = 0;     //Reset error
  frame->payload.w.w2 = can_elapsed_ms;
  return 0;
}

// CAN receive frame count global variables:
extern volatile unsigned short can_rx_frame_count_1;
extern volatile unsigned short can_rx_frame_count_2;
extern volatile unsigned short can_rx_frame_count_3;
extern volatile unsigned short can_rx_frame_count_4;

/*
// CAN error storage ring buffer, non-ISR
const unsigned short can_error_buffer_size = 10;
unsigned short can_error_type_buffer[can_error_buffer_size];
unsigned short can_error_freq_buffer[can_error_buffer_size];
unsigned long can_error_time_buffer[can_error_buffer_size];
unsigned short can_error_write_index = 0; // when write_index = read_index, no errors.
unsigned short can_error_read_index = 0;

// CAN error storage ring buffer, IRQ
const unsigned short can_error_irq_buffer_size = 10;
unsigned short can_error_type_irq_buffer[can_error_buffer_size];
unsigned short can_error_freq_irq_buffer[can_error_buffer_size];
unsigned long can_error_time_irq_buffer[can_error_buffer_size];
unsigned short can_error_write_irq_index = 0; // when write_index = read_index, no errors.
unsigned short can_error_read_irq_index = 0;

unsigned short can_get_error(CAN_FRAME * frame_ptr)
{
  static unsigned short irq_first = 0;

  if (irq_first) //Check first the IRQ buffer for errors, then the normal buffer
  {
    irq_first = 0;  // Toggle irq_first value, so both buffers have a chance to be read eventually
    if (!can_error_irq_pop(frame_ptr))
    {
      return 0; // Error data popped from buffer successfully
    }
    if (!can_error_pop(frame_ptr))
    {
      return 0; // Error data popped from buffer successfully
    }
  }
  else  //Check first the normal buffer for errors, then the IRQ buffer
  {
    irq_first = 1;  // Toggle irq_first value, so both buffers have a chance to be read eventually
    if (!can_error_pop(frame_ptr))
    {
      return 0; // Error data popped from buffer successfully
    }
    if (!can_error_irq_pop(frame_ptr))
    {
      return 0; // Error data popped from buffer successfully
    }
  }

  return 1; // No error data in buffers
}

unsigned short can_error_irq_pop(CAN_FRAME * frame)
{
  if (can_error_read_irq_index != can_error_write_irq_index)
  {
    frame->payload.w.w1 = can_error_type_irq_buffer[can_error_read_irq_index];       // Start with the basic ERROR_ID
    frame->payload.w.w1 |= (can_error_freq_irq_buffer[can_error_read_irq_index] & 0xFF) << 13;  // OR in the frequency value
    frame->payload.w.w2 = can_error_time_irq_buffer[can_error_read_irq_index];  // Include timestamp of error

    //advance error ring buffer read index
    if (can_error_read_irq_index >= (can_error_irq_buffer_size - 1))
    {
      can_error_read_irq_index = 0;  // wrap around to zero
    }
    else
    {
      ++can_error_read_irq_index; // increment
    }
    return 0; // Error data popped from buffer successfully
  }
  return 1; // No error data in ring buffer
}

unsigned short can_error_pop(CAN_FRAME * frame)
{
  if (can_error_read_index != can_error_write_index)
  {
    frame->payload.w.w1 = can_error_type_buffer[can_error_read_index];       // Start with the basic ERROR_ID
    frame->payload.w.w1 |= (can_error_freq_buffer[can_error_read_index] & 0xFF) << 13;  // OR in the frequency value
    frame->payload.w.w2 = can_error_time_buffer[can_error_read_index];  // Include timestamp of error

    //advance error ring buffer read index
    if (can_error_read_index >= (can_error_buffer_size - 1))
    {
      can_error_read_index = 0;  // wrap around to zero
    }
    else
    {
      ++can_error_read_index; // increment
    }
    return 0; // Error data popped from buffer successfully
  }
  return 1; // No error data in ring buffer
}

void can_error_irq_push(unsigned short err)
{
  unsigned short temp_index = can_error_read_irq_index;

  while (temp_index != can_error_write_irq_index)
  {
    if (can_error_type_irq_buffer[temp_index] == err) // Error match found to exist already in buffer
    {
      ++can_error_freq_irq_buffer[temp_index];   // Increment frequency value
      can_error_time_irq_buffer[temp_index] = can_elapsed_ms; // Update time value (most recent occurrence)
      return; // No need to search further, error update is done.
    }
    if (++temp_index >= can_error_irq_buffer_size)
    {
      temp_index = 0; // Wrap around to zero in ring buffer
    }
  }

  temp_index = can_error_write_irq_index;

  //No ERROR_ID match found in buffer, push new one on
  can_error_type_irq_buffer[temp_index] = err;
  can_error_freq_irq_buffer[temp_index] = 1;   // This is the first error of this type.
  can_error_time_irq_buffer[temp_index] = can_elapsed_ms;

  if (++temp_index >= can_error_irq_buffer_size)
  {
    temp_index = 0;  // Wrap around to zero in ring buffer
  }
  if (temp_index != can_error_read_irq_index)
  {
    can_error_write_irq_index = temp_index;
  }
  // else //error - this should only be able to happen if the buffer size is smaller than
  // the number of CAN ERROR_IDs possible.
} 

void can_error_push(unsigned short err)
{
  unsigned short temp_index = can_error_read_index;

  while (temp_index != can_error_write_index)
  {
    if (can_error_type_buffer[temp_index] == err) // Error match found to exist already in buffer
    {
      ++can_error_freq_buffer[temp_index];   // Increment frequency value
      can_error_time_buffer[temp_index] = can_elapsed_ms; // Update time value (most recent occurrence)
      return; // No need to search further, error update is done.
    }
    if (++temp_index >= can_error_buffer_size)
    {
      temp_index = 0; // Wrap around to zero in ring buffer
    }
  }

  temp_index = can_error_write_index;

  //No ERROR_ID match found in buffer, push new one on
  can_error_type_buffer[temp_index] = err;
  can_error_freq_buffer[temp_index] = 1;   // This is the first error of this type.
  can_error_time_buffer[temp_index] = can_elapsed_ms;

  if (++temp_index >= can_error_buffer_size)
  {
    temp_index = 0;  // Wrap around to zero in ring buffer
  }
  if (temp_index != can_error_read_index)
  {
    can_error_write_index = temp_index;
  }
  // else //error - this should only be able to happen if the buffer size is smaller than
  // the number of CAN ERROR_IDs possible.
} 
*/
unsigned short can_set_elapsed_ms(CAN_FRAME * frame)
{
  can_elapsed_ms = frame->payload.w.w2;
  return 0;
} 

void can_rx1_isr(void)__irq{
//  volatile int can1icr = C1ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif 
  ++can_rx_frame_count_1; // Count received frame
  can_rx_now(CHAN_CAN1);//Get and dispatch received frame
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_rx2_isr(void)__irq{
 // volatile int can2icr = C2ICR;
  
    #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif
  ++can_rx_frame_count_2; // Count received frame
  can_rx_now(CHAN_CAN2);//Get and dispatch received frame
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_rx3_isr(void)__irq{
//  volatile int can3icr = C3ICR;
  
    #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif
  ++can_rx_frame_count_3; // Count received frame
  can_rx_now(CHAN_CAN3);//Get and dispatch received frame
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_rx4_isr(void)__irq{
//  volatile int can4icr = C4ICR;
  
    #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif
  ++can_rx_frame_count_4; // Count received frame
  can_rx_now(CHAN_CAN4);//Get and dispatch received frame
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

/*
void can_tx1_isr(void)__irq
{
  volatile int can1icr = C1ICR;
  #ifdef DEBUG
      if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  can_tx_send_next_frame(CHAN_CAN1);  
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx2_isr(void)__irq
{
  volatile int can2icr = C2ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  can_tx_send_next_frame(CHAN_CAN2);
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx3_isr(void)__irq
{
  volatile int can1icr = C3ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  can_tx_send_next_frame(CHAN_CAN3);
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx4_isr(void)__irq
{
  volatile int can1icr = C4ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  can_tx_send_next_frame(CHAN_CAN4);
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}
*/
/*
void can_tx1_isr(void)__irq
{

  volatile int can1icr = C1ICR;
  #ifdef DEBUG
      if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif
  
  // Callback function to keep track of transmit frame quantities on each channel
  (*can_tx_frame_count)(CHAN_CAN1); //Problem: this is only called if the isr fires, not if stalled.
  can_tx_send_next_frame(CHAN_CAN1);  
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx2_isr(void)__irq
{
  volatile int can2icr = C2ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  // Callback function to keep track of transmit frame quantities on each channel
  (*can_tx_frame_count)(CHAN_CAN2);
  can_tx_send_next_frame(CHAN_CAN2);
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx3_isr(void)__irq
{
  volatile int can1icr = C3ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  // Callback function to keep track of transmit frame quantities on each channel
  (*can_tx_frame_count)(CHAN_CAN3);
  can_tx_send_next_frame(CHAN_CAN3);
  VICVectAddr = 0;    // Clear interrupt in VIC. 
}

void can_tx4_isr(void)__irq
{
  volatile int can1icr = C4ICR;
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif
  // Callback function to keep track of transmit frame quantities on each channel
  (*can_tx_frame_count)(CHAN_CAN4);
  can_tx_send_next_frame(CHAN_CAN4);
  VICVectAddr = 0;    // Reset interrupt address in VIC. 
}
*/

void can_error_isr(void) __irq
{
 volatile int can_status1; //save state of capture register
 volatile int can_status2; //save state of capture register
 volatile int can_status3; //save state of capture register
 volatile int can_status4; //save state of capture register
 
 volatile unsigned long can_acc_filter_error;   //save location of error in AF lookup table
  
  #ifdef DEBUG
    if (FIO0PIN & 1<<14)
    {
      VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
      VICVectAddr = 0;
      return;
    }
  #endif

  if (LUTerr & (1<<0))
  {
    can_acc_filter_error = LUTerrAd;  // Address in look-up table RAM (AF) at which error was encountered
                                      // Reading this register clears LUTerr error flag
    error_occurred_irq(ERROR_CAN_ACC_FILTER);  // Acceptance filter error - most likely a table error
  }

#ifdef USE_CAN1
  if (C1GSR & (1<<7))
  { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
    C1MOD = 0; //restart the can bus
    error_occurred_irq(ERROR_CAN1_TX_BUSOFF);  // Transmit errors leading to bus off error state
    can_error_1 = ERROR_CAN1_TX_BUSOFF;
    //can_tx_send_next_frame(CHAN_CAN1); //start the transmissions again
    //VICSoftInt = 1<<20;   //Force CAN1 TX interrupt     // **** TEST CODE ****
  }
  can_status1 = C1ICR; //save state of capture register
    if (can_status1 & ((1<<2)|(1<<3)|(1<<5)|(1<<7)))
  {
    if (can_status1 & (1<<2))
    {
      can_error_1 = ERROR_CAN1_ERR_WARN;
      error_occurred_irq(ERROR_CAN1_ERR_WARN);  // Shows change in error or bus status bits in either direction
    }
    if (can_status1 & (1<<3))
    {
      can_error_1 = ERROR_CAN1_DATA_OVRN;
      error_occurred_irq(ERROR_CAN1_DATA_OVRN);  // Receive data overrun on CAN1 - receive buffer not read before
                                                    // arrival of next received frame, data lost
    }
    if (can_status1 & (1<<5))
    {
      can_error_1 = ERROR_CAN1_ERR_PASS;
      error_occurred_irq(ERROR_CAN1_ERR_PASS);  // Shows change in active or passive error status in either direction
    }
    if (can_status1 & (1<<7))
    {
      if (can_status1 & (1<<21))
      {
        can_error_1 = ERROR_CAN1_BUS_RX;
        error_occurred_irq(ERROR_CAN1_BUS_RX);  // CAN1 has detected an rx bus error. Details of the error require reading
                                                  // the other bits in can_status1. For now that has to be done in the debugger,
                                                  // including all the possiblities in the ERROR_IDs would be cumbersome.
                                                  // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
      }                                           // if we wanted.
      else
      {
         can_error_1 = ERROR_CAN1_BUS_TX;
         error_occurred_irq(ERROR_CAN1_BUS_TX);
      }
    }
  } 
#endif

#ifdef USE_CAN2
  if (C2GSR & (1<<7))
  { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
    C2MOD = 0; //restart the can bus
    error_occurred_irq(ERROR_CAN2_TX_BUSOFF);  // Transmit errors leading to bus off error state
    can_error_2 = ERROR_CAN2_TX_BUSOFF;
   // can_tx_send_next_frame(CHAN_CAN2); //start the transmissions again
    //VICSoftInt = 1<<21;   //Force CAN2 TX interrupt     // **** TEST CODE ****
  }
  can_status2 = C2ICR; //save state of capture register
  if (can_status2 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
  {
    if (can_status2 & (1<<2))
    {
      can_error_2 = ERROR_CAN2_ERR_WARN;
      error_occurred_irq(ERROR_CAN2_ERR_WARN);  // Shows change in error or bus status bits in either direction
    }
    if (can_status2 & (1<<3))
    {
      can_error_2 = ERROR_CAN2_DATA_OVRN;
      error_occurred_irq(ERROR_CAN2_DATA_OVRN);  // Receive data overrun on CAN2 - receive buffer not read before
                                                    // arrival of next received frame, data lost
    }
    if (can_status2 & (1<<5))
    {
      can_error_2 = ERROR_CAN2_ERR_PASS;
      error_occurred_irq(ERROR_CAN2_ERR_PASS);  // Shows change in active or passive error status in either direction
    }
    if (can_status2 & (1<<7))
    {
      if (can_status2 & (1<<21))
      {
        can_error_2 = ERROR_CAN2_BUS_RX;
        error_occurred_irq(ERROR_CAN2_BUS_RX);  // CAN2 has detected an rx bus error. Details of the error require reading
                                                  // the other bits in can_status1. For now that has to be done in the debugger,
                                                  // including all the possiblities in the ERROR_IDs would be cumbersome.
                                                  // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
                                                  // if we wanted.
      }
      else
      {
        can_error_2 = ERROR_CAN2_BUS_TX;
         error_occurred_irq(ERROR_CAN2_BUS_TX);
      }
    }
  }
#endif

#ifdef USE_CAN3
  if (C3GSR & (1<<7))
  { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
    C3MOD = 0; //restart the can bus
    error_occurred_irq(ERROR_CAN3_TX_BUSOFF);  // Transmit errors leading to bus off error state
    can_error_3 = ERROR_CAN3_TX_BUSOFF;
    //can_tx_send_next_frame(CHAN_CAN3); //start the transmissions again
    //VICSoftInt = 1<<22;   //Force CAN3 TX interrupt     // **** TEST CODE ****
  } 
  can_status3 = C3ICR; //save state of capture register
  if (can_status3 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
  {
    if (can_status3 & (1<<2))
    {
      can_error_3 = ERROR_CAN3_ERR_WARN;
      error_occurred_irq(ERROR_CAN3_ERR_WARN);  // Shows change in error or bus status bits in either direction
    }
    if (can_status3 & (1<<3))
    {
      can_error_3 = ERROR_CAN3_DATA_OVRN;
      error_occurred_irq(ERROR_CAN3_DATA_OVRN);  // Receive data overrun on CAN3 - receive buffer not read before
                                                    // arrival of next received frame, data lost
    }
    if (can_status3 & (1<<5))
    {
      can_error_3 = ERROR_CAN3_ERR_PASS;
      error_occurred_irq(ERROR_CAN3_ERR_PASS);  // Shows change in active or passive error status in either direction
    }
    if (can_status3 & (1<<7))
    {
      if (can_status3 & (1<<21))
      {
        can_error_3 = ERROR_CAN3_BUS_RX;
        error_occurred_irq(ERROR_CAN3_BUS_RX);  // CAN3 has detected an rx bus error. Details of the error require reading
                                                  // the other bits in can_status1. For now that has to be done in the debugger,
                                                  // including all the possiblities in the ERROR_IDs would be cumbersome.
                                                  // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
                                                  // if we wanted.
      }
      else
      {
         can_error_3 = ERROR_CAN3_BUS_TX;
         error_occurred_irq(ERROR_CAN3_BUS_TX);
      }
    }
  }
#endif

#ifdef USE_CAN4
  if (C4GSR & (1<<7))
  { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
    C4MOD = 0; //restart the can bus
    error_occurred_irq(ERROR_CAN4_TX_BUSOFF);  // Transmit errors leading to bus off error state
    can_error_4 = ERROR_CAN4_TX_BUSOFF;
   // can_tx_send_next_frame(CHAN_CAN4); //start the transmissions again
   // VICSoftInt = 1<<23;   //Force CAN4 TX interrupt     // **** TEST CODE ****
  }
  can_status4 = C4ICR; //save state of capture register 
  
  if (can_status4 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
  {
    if (can_status4 & (1<<2))
    {
      can_error_4 = ERROR_CAN4_ERR_WARN;
      error_occurred_irq(ERROR_CAN4_ERR_WARN);  // Shows change in error or bus status bits in either direction
    }
    if (can_status4 & (1<<3))
    {
      can_error_4 = ERROR_CAN4_DATA_OVRN;
      error_occurred_irq(ERROR_CAN4_DATA_OVRN);  // Receive data overrun on CAN4 - receive buffer not read before
                                                    // arrival of next received frame, data lost
    }
    if (can_status4 & (1<<5))
    {
      can_error_4 = ERROR_CAN4_ERR_PASS;
      error_occurred_irq(ERROR_CAN4_ERR_PASS);  // Shows change in active or passive error status in either direction
    }
    if (can_status4 & (1<<7))
    {
      if (can_status4 & (1<<21))
      {
        can_error_4 = ERROR_CAN4_BUS_RX;
        error_occurred_irq(ERROR_CAN4_BUS_RX);  // CAN4 has detected an rx bus error. Details of the error require reading
                                                  // the other bits in can_status1. For now that has to be done in the debugger,
                                                  // including all the possiblities in the ERROR_IDs would be cumbersome.
                                                  // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
                                                  // if we wanted.
      }
      else
      {
        can_error_4 = ERROR_CAN4_BUS_TX;
        error_occurred_irq(ERROR_CAN4_BUS_TX);
      }
    }
  }
 #endif
  //To do? Put software interrupt force bits for all tx channels here? What about 2-channel MCUs vs. 4-channel?

  VICVectAddr = 0;
}

// Default function for callback functions of type void int,
// to avoid problems with calling a non-initialized function pointer
void can_voidint(unsigned short chan)
{
}