00001 #include <includes.h> 00002 00003 00004 #define SCHEDULE_TICK_DIVIDER 1 //number of system jiffies (should be 1 mS) per time slot 00005 #define SCHEDULE_TICKS_PER_MS 1 //number of ticks per millisecond 00006 00007 #define RUN_EVERY_LINE (TASK_PTR)&b10a_update_can_leds, (TASK_PTR)&b10a_update_mcu_leds, (TASK_PTR)&error_update, (TASK_PTR)&hb_beat_count 00008 const TASK_PTR schedule[]= 00009 { 00010 RUN_EVERY_LINE, (TASK_PTR)&error_send_next, (TASK_PTR)NULL, 00011 RUN_EVERY_LINE, (TASK_PTR)NULL, 00012 RUN_EVERY_LINE, (TASK_PTR)NULL, 00013 RUN_EVERY_LINE, (TASK_PTR)NULL, 00014 RUN_EVERY_LINE, (TASK_PTR)NULL, 00015 RUN_EVERY_LINE, (TASK_PTR)NULL, 00016 RUN_EVERY_LINE, (TASK_PTR)NULL, 00017 RUN_EVERY_LINE, (TASK_PTR)NULL, 00018 RUN_EVERY_LINE, (TASK_PTR)NULL, 00019 RUN_EVERY_LINE, (TASK_PTR)NULL, 00020 (TASK_PTR)NULL 00021 }; 00022 00024 00025 /* 00026 // ********************************CAN********************************* 00027 #define CAN_RX_FRAME_BUF_LEN 64 00028 CAN_RING can_rx_ring; 00029 CAN_FRAME can_rx_frame_buf[CAN_RX_FRAME_BUF_LEN]; 00030 00031 #define CAN_TX_FRAME_BUF_LEN 8 00032 CAN_RING can_tx_ring1; 00033 CAN_FRAME can_tx_frame_buf1[CAN_TX_FRAME_BUF_LEN]; 00034 CAN_RING can_tx_ring2; 00035 CAN_FRAME can_tx_frame_buf2[CAN_TX_FRAME_BUF_LEN]; 00036 CAN_RING can_tx_ring3; 00037 CAN_FRAME can_tx_frame_buf3[CAN_TX_FRAME_BUF_LEN]; 00038 CAN_RING can_tx_ring4; 00039 CAN_FRAME can_tx_frame_buf4[CAN_TX_FRAME_BUF_LEN]; 00040 00042 */ 00043 00044 void heartbeat_blink_blue(void) 00045 { 00046 b10a_mcu_blue_led_blink(50); 00047 } 00048 00049 void setup_software(void) 00050 { 00051 /********************************************* 00052 * Scheduler Initialization. Do not modify. * 00053 *********************************************/ 00054 asched_init(schedule,SCHEDULE_TICK_DIVIDER); 00055 00056 /********************************************* 00057 * Put user initialization code below here. * 00058 *********************************************/ 00059 error_init(router_error_transmit, asched_get_timestamp); 00060 hb_init(500, &heartbeat_blink_blue, asched_get_timestamp); 00061 00062 //Zero out global variables. Buffer indexes can be corrupted during debugger operation 00063 csr_global_variable_init(); 00064 00065 00066 //set_heartbeat_period_ms(250); 00067 00068 // Initialize CAN router board functions and buffers 00069 router_data_nexus_init(); 00070 00071 csr_routing_table_init(); // initialize routing table to default values 00072 00073 //can_rx_acceptance_filter_init(); 00074 00075 //csr_enable_chan(CHAN_CAN1); 00076 //csr_enable_chan(CHAN_CAN2); 00077 00078 // ******************************************* 00079 // Set up CAN 00080 // ******************************************* 00081 00082 // Select functions to be called when can_isr receieves a CAN frame, transmits a frame, or has an error. 00083 // Functions must take the CAN channel number (1 - 4) as an argument. 00084 // To do: make the error callback function more detailed. 00085 can_init_status_callback(&b10a_can_packet_count, // Count received frame on a given CAN channel 00086 &b10a_can_packet_count, // Count transmitted frame on a given CAN channel 00087 &b10a_blink_red_can_led); // Error on a given CAN channel 00088 /* 00089 can_rx_set_descriptors(NULL, NULL); 00090 can_ring_init(&can_rx_ring, can_rx_frame_buf, CAN_RX_FRAME_BUF_LEN); 00091 00092 // ********* CAN1 *********** 00093 can_ring_init(&can_tx_ring1, can_tx_frame_buf1, CAN_TX_FRAME_BUF_LEN); 00094 can_tx_set_chan_cfg(CHAN_CAN1, (volatile unsigned long *)0xE0044000, &can_tx_ring1); 00095 can_rx_set_chan_cfg(CHAN_CAN1, (volatile unsigned long *)0xE0044000, &can_rx_ring, CAN_DISPATCH_MANUAL); 00096 00097 // ******** CAN2 *********** 00098 can_ring_init(&can_tx_ring2,can_tx_frame_buf2,CAN_TX_FRAME_BUF_LEN); 00099 can_tx_set_chan_cfg(CHAN_CAN2, (volatile unsigned long *)0xE0048000, &can_tx_ring2); 00100 can_rx_set_chan_cfg(CHAN_CAN2, (volatile unsigned long *)0xE0048000, &can_rx_ring,CAN_DISPATCH_MANUAL); 00101 00102 // ******** CAN3 *********** 00103 can_ring_init(&can_tx_ring3, can_tx_frame_buf3, CAN_TX_FRAME_BUF_LEN); 00104 can_tx_set_chan_cfg(CHAN_CAN3, (volatile unsigned long *)0xE004C000, &can_tx_ring3); 00105 can_rx_set_chan_cfg(CHAN_CAN3, (volatile unsigned long *)0xE004C000, &can_rx_ring,CAN_DISPATCH_MANUAL); 00106 00107 // ******** CAN4 *********** 00108 can_ring_init(&can_tx_ring4, can_tx_frame_buf4, CAN_TX_FRAME_BUF_LEN); 00109 can_tx_set_chan_cfg(CHAN_CAN4, (volatile unsigned long *)0xE0050000, &can_tx_ring4); 00110 can_rx_set_chan_cfg(CHAN_CAN4,(volatile unsigned long *)0xE0050000,&can_rx_ring,CAN_DISPATCH_MANUAL); 00111 00112 csr_init_can_rx_ring(&can_rx_ring); 00113 */ 00114 /* 00115 // ******************************************* 00116 // Set up CAN/SSP Router 00117 // ******************************************* 00118 csr_init(&can_rx_ring); 00119 00120 csr_enable_chan(CHAN_SSP); 00121 csr_enable_chan(CHAN_CAN1); 00122 csr_enable_chan(CHAN_CAN2); 00123 csr_enable_chan(CHAN_CAN3); 00124 csr_enable_chan(CHAN_CAN4); 00125 */ 00126 00127 //Synchronize with ARM9 board. Execution will wait here until two ready codes 00128 //have been successfully exchanged with the ARM9. This function should be called 00129 //immediately prior to enabling of the interrupts. 00130 //csr_synchronize_arm9(); 00131 00133 //Enable interrupts 00135 VICIntEnable = 0; 00136 VICVectAddr = 0; 00137 VICSoftIntClr = 0xffffffff; //clear all interupts - only do this once 00138 00139 00140 //SSP and associated Timer1 interrupt setup FIQ 00141 VICIntSelect |= 1 << 11; //Enable FIQ interrupts for SSP 00142 VICIntSelect |= 1 << 5; //Enable FIQ interrupts for Timer1 00143 VICIntEnable = 1 << 11; // Enable SSP interrupt 00144 VICIntEnable = 1 << 5; // Enable Timer1 interrupt 00145 T1TCR = 1; //Start Timer1 00146 00147 00148 00149 // ************ PRIORITY 0 ****************** 00150 //Timer0 interrupt setup 00151 VICVectAddr0 = (unsigned long)timer0_isr; 00152 VICVectCntl0 = 0x20 | 4; /* Timer0 Interrupt */ 00153 VICIntEnable = 1 << 4; /* Enable Timer0 Interrupt */ 00154 00155 // ************ PRIORITY 1 ****************** 00156 //UART (uart_int) 00157 // VICVectAddr1 = (unsigned long)uarti_isr; 00158 // VICVectCntl1 = 0x20 | VIC_UART1; 00159 // VICIntEnable = 1 << VIC_UART1; 00160 00161 00162 00163 // ************ PRIORITY 2 ****************** 00164 //CAN1 RX 00165 VICVectAddr2 = (unsigned long)can_rx1_isr; 00166 VICVectCntl2 = 0x20 | VIC_CAN1RX; 00167 VICIntEnable = 1 << VIC_CAN1RX; 00168 00169 // ************ PRIORITY 3 ****************** 00170 //CAN1 TX 00171 // VICVectAddr3 = (unsigned long)csr_can1_tx_isr; 00172 VICVectAddr3 = (unsigned long)can_tx1_isr; 00173 VICVectCntl3 = 0x20 | VIC_CAN1TX; 00174 VICIntEnable = 1 << VIC_CAN1TX; 00175 00176 // ************ PRIORITY 4 ****************** 00177 //CAN2 RX 00178 VICVectAddr4 = (unsigned long)can_rx2_isr; 00179 VICVectCntl4 = 0x20 | VIC_CAN2RX; 00180 VICIntEnable = 1 << VIC_CAN2RX; 00181 00182 // ************ PRIORITY 5 ****************** 00183 //CAN2 TX 00184 // VICVectAddr5 = (unsigned long)csr_can2_tx_isr; 00185 VICVectAddr5 = (unsigned long)can_tx2_isr; 00186 VICVectCntl5 = 0x20 | VIC_CAN2TX; 00187 VICIntEnable = 1 << VIC_CAN2TX; 00188 00189 // ************ PRIORITY 6 ****************** 00190 //CAN3 RX 00191 VICVectAddr6 = (unsigned long)can_rx3_isr; 00192 VICVectCntl6 = 0x20 | VIC_CAN3RX; 00193 VICIntEnable = 1 << VIC_CAN3RX; 00194 00195 // ************ PRIORITY 7 ****************** 00196 //CAN3 TX 00197 VICVectAddr7 = (unsigned long)can_tx3_isr; 00198 // VICVectAddr7 = (unsigned long)csr_can3_tx_isr; 00199 VICVectCntl7 = 0x20 | VIC_CAN3TX; 00200 VICIntEnable = 1 << VIC_CAN3TX; 00201 00202 // ************ PRIORITY 8 ****************** 00203 //CAN4 RX 00204 VICVectAddr8 = (unsigned long)can_rx4_isr; 00205 VICVectCntl8 = 0x20 | VIC_CAN4RX; 00206 VICIntEnable = 1 << VIC_CAN4RX; 00207 00208 // ************ PRIORITY 9 ****************** 00209 //CAN4 TX 00210 // VICVectAddr9 = (unsigned long)csr_can4_tx_isr; 00211 VICVectAddr9 = (unsigned long)can_tx4_isr; 00212 VICVectCntl9 = 0x20 | VIC_CAN4TX; 00213 VICIntEnable = 1 << VIC_CAN4TX; 00214 00215 // ************ PRIORITY 10 ****************** 00216 //CAN common (for error handling) 00217 VICVectAddr10 = (unsigned long)can_error_isr; 00218 VICVectCntl10 = 0x20 | 19; 00219 VICIntEnable = 1 << 19; 00220 00221 00222 //UART0 interrupt setup 00223 //VICVectCntl3 = (1<<5) + 6; //Enable vectored interrupt slot 3 and set it to UART0 (interrupt source 6) 00224 // VICIntSelect &= ~(1<<6); //Clear bit 6 - use IRQ interrupts for UART0, not FIQ. 00225 //VICIntEnable = 1<<6; //Enable UART0 interrupt at vectored interrupt controller (VIC) 00226 // } 00227 }