rc_receive.h

00001 #ifndef __RC_RECEIVE_H__
00002 #define __RC_RECEIVE_H__
00003 
00007 typedef struct rcx_data{
00008   int prev; 
00009   int start; 
00010   int value; 
00011   int overflows; 
00012 } RCX_DATA;
00013 
00017 typedef enum rcx_channels{
00018   RCX_CHAN_0 = 0,
00019   RCX_CHAN_1,
00020   RCX_CHAN_2,
00021   RCX_CHAN_3,
00022   RCX_LAST
00023 } RCX_CHAN;
00024 
00025 //Functions
00026 void rcx_init(int chan_0, int chan_1, int chan_2, int chan_3);
00027 void rcx_isr(void);//__irq;
00028 float rcx_get_chan_0(void);
00029 float rcx_get_chan_1(void);
00030 float rcx_get_chan_2(void);
00031 float rcx_get_chan_3(void);
00032 float rcx_get_chan(RCX_CHAN chan);
00033 static void rcx_update(RCX_CHAN chan, int curr, int cap_value, int flag_overflow);
00034 
00035 /* HARDWARE SETUP
00036   // *******************************************************************************
00037   // RC Receive Setup
00038   // *******************************************************************************
00039   PINSEL1 &= ~(3<<12); //p0.22 clear
00040   PINSEL1 &= ~(3<<22); //p0.27 clear
00041 //  PINSEL1 &= ~(3<<0); //p0.16  clear
00042 //  PINSEL1 &= ~(3<<26); //p0.29 clear
00043   PINSEL1 |= (2<<12); //p0.22 cap0
00044   PINSEL1 |= (2<<22); //p0.27 cap1
00045 //  PINSEL1 |= (3<<0); //p0.16 cap2
00046 //  PINSEL1 |= (2<<26); //p0.29 cap3
00047   T0IR = 0xFF;
00048   T0CCR |= (1<<0)|(1<<1)|(1<<2); //cap0 interrupt on RE (rising edge) and FE (falling edge)
00049   T0CCR |= (1<<3)|(1<<4)|(1<<5); //cap1 interrupt on RE (rising edge) and FE (falling edge)
00050 //  T0CCR |= (1<<6)|(1<<7)|(1<<8); //cap2 interrupt on RE (rising edge) and FE (falling edge)
00051 //  T0CCR |= (1<<9)|(1<<10)|(1<<11); //cap3 interrupt on RE (rising edge) and FE (falling edge)
00052   T0MR0 = (60000000/100)-1; //10ms       
00053   T0MCR = (1<<0)|(1<<1); // Match Control Reg: Interrupt(b0) and Reset(b1) on MR0;
00054   T0TCR = 1;   // Timer0 Enable
00055 */
00056 
00057 #endif  //__RC_RECEIVE_H__
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