csr_can_tx.c

00001 #include <includes.h>
00002 
00003 // CAN error global variables:
00004 volatile unsigned long can_error_1 = 0;
00005 volatile unsigned long can_error_2 = 0;
00006 volatile unsigned long can_error_3 = 0;
00007 volatile unsigned long can_error_4 = 0;
00008 
00009 // CAN receive frame count global variables:
00010 volatile unsigned short can_rx_frame_count_1 = 0;
00011 volatile unsigned short can_rx_frame_count_2 = 0;
00012 volatile unsigned short can_rx_frame_count_3 = 0;
00013 volatile unsigned short can_rx_frame_count_4 = 0;
00014 
00015 // CAN transmit frame count global variables:
00016 volatile unsigned short can_tx_frame_count_1 = 0;
00017 volatile unsigned short can_tx_frame_count_2 = 0;
00018 volatile unsigned short can_tx_frame_count_3 = 0;
00019 volatile unsigned short can_tx_frame_count_4 = 0;
00020 
00021 //Set up CAN transmit buffers (version 2)
00022 #define CSR_CAN_TX_BUFFER_SIZE  8
00023 volatile CAN_FRAME csr_can1_tx_buffer[CSR_CAN_TX_BUFFER_SIZE];
00024 volatile short int csr_can1_tx_index1 = 0;
00025 volatile short int csr_can1_tx_index2 = 0;
00026 
00027 volatile CAN_FRAME csr_can2_tx_buffer[CSR_CAN_TX_BUFFER_SIZE];
00028 volatile short int csr_can2_tx_index1 = 0;
00029 volatile short int csr_can2_tx_index2 = 0;
00030 
00031 volatile CAN_FRAME csr_can3_tx_buffer[CSR_CAN_TX_BUFFER_SIZE];
00032 volatile short int csr_can3_tx_index1 = 0;
00033 volatile short int csr_can3_tx_index2 = 0;
00034 
00035 volatile CAN_FRAME csr_can4_tx_buffer[CSR_CAN_TX_BUFFER_SIZE];
00036 volatile short int csr_can4_tx_index1 = 0;
00037 volatile short int csr_can4_tx_index2 = 0;
00038 
00039 //Set up CAN receive buffers (version 2)
00040 #define CSR_CAN_RX_BUFFER_SIZE  64
00041 volatile CAN_FRAME csr_can_rx_buffer[CSR_CAN_RX_BUFFER_SIZE];
00042 volatile short int csr_can_rx_index1 = 0;
00043 volatile short int csr_can_rx_index2 = 0;
00044 
00045 unsigned short csr_can_rx_pop_frame(CAN_FRAME * frameptr)
00046 {
00047   volatile short int temp_index1 = csr_can_rx_index1;
00048   volatile short int temp_index2 = csr_can_rx_index2;
00049 
00050   if (temp_index2 != temp_index1)
00051   {
00052     *frameptr = csr_can_rx_buffer[temp_index2];
00053     if (++temp_index2 >= CSR_CAN_RX_BUFFER_SIZE) 
00054     {
00055       temp_index2 = 0;
00056     }
00057     csr_can_rx_index2 = temp_index2;  // Update read index
00058     return 0; // Frame popped successfully
00059   }
00060   else
00061   {
00062     return 1; // Buffer empty
00063   }
00064 }
00065 
00067 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00068 void csr_can_rx1_fiq(void)
00069 {
00070   short int temp_index = csr_can_rx_index1;
00071 
00072   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00073   if (temp_index == csr_can_rx_index2)
00074   {
00075     //Buffer full, new data will be lost; don't advance write index
00076     error_occurred_fiq(ERROR_CAN1_RX_BUF_OF);  
00077     C1CMR = 1<<2; //Release CAN data buffer
00078     return;
00079   }
00080   ++can_rx_frame_count_1; // Count received frame
00081 
00082   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN1;
00083   csr_can_rx_buffer[temp_index].addr            = C1RID;
00084   csr_can_rx_buffer[temp_index].dlc             = (C1RFS>>16)&0xF;
00085   csr_can_rx_buffer[temp_index].rtr             = (C1RFS>>30)&0x1;
00086   csr_can_rx_buffer[temp_index].payload.w.w1    = C1RDA;
00087   csr_can_rx_buffer[temp_index].payload.w.w2    = C1RDB;
00088    
00089   C1CMR = 1<<2; //Release CAN data buffer 
00090     
00091   csr_can_rx_index1 = temp_index;   //update index1
00092 }
00094 
00096 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00097 void csr_can_rx2_fiq(void)
00098 {
00099   short int temp_index = csr_can_rx_index1;
00100 
00101   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00102   if (temp_index == csr_can_rx_index2)
00103   {
00104     //Buffer full, new data will be lost; don't advance write index
00105     error_occurred_fiq(ERROR_CAN2_RX_BUF_OF);  
00106     C2CMR = 1<<2; //Release CAN data buffer
00107     return;
00108   }
00109   ++can_rx_frame_count_2; // Count received frame
00110 
00111   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN2;
00112   csr_can_rx_buffer[temp_index].addr            = C2RID;
00113   csr_can_rx_buffer[temp_index].dlc             = (C2RFS>>16)&0xF;
00114   csr_can_rx_buffer[temp_index].rtr             = (C2RFS>>30)&0x1;
00115   csr_can_rx_buffer[temp_index].payload.w.w1    = C2RDA;
00116   csr_can_rx_buffer[temp_index].payload.w.w2    = C2RDB; 
00117 
00118   C2CMR = 1<<2; //Release CAN data buffer 
00119    
00120   csr_can_rx_index1 = temp_index;   //update index1
00121 }
00123 
00125 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00126 void csr_can_rx3_fiq(void)
00127 {
00128   short int temp_index = csr_can_rx_index1;
00129 
00130   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00131   if (temp_index == csr_can_rx_index2)
00132   {
00133     //Buffer full, new data will be lost; don't advance write index
00134     error_occurred_fiq(ERROR_CAN3_RX_BUF_OF);  
00135     C3CMR = 1<<2; //Release CAN data buffer
00136     return;
00137   }
00138 
00139   ++can_rx_frame_count_3; // Count received frame
00140 
00141   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN3;
00142   csr_can_rx_buffer[temp_index].addr            = C3RID;
00143   csr_can_rx_buffer[temp_index].dlc             = (C3RFS>>16)&0xF;
00144   csr_can_rx_buffer[temp_index].rtr             = (C3RFS>>30)&0x1;
00145   csr_can_rx_buffer[temp_index].payload.w.w1    = C3RDA;
00146   csr_can_rx_buffer[temp_index].payload.w.w2    = C1RDB;
00147   
00148   C3CMR = 1<<2; //Release CAN data buffer 
00149    
00150   csr_can_rx_index1 = temp_index;   //update index1
00151 }
00153 
00155 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00156 void csr_can_rx4_fiq(void)
00157 {
00158   short int temp_index = csr_can_rx_index1;
00159 
00160   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00161   if (temp_index == csr_can_rx_index2)
00162   {
00163     //Buffer full, new data will be lost; don't advance write index
00164     error_occurred_fiq(ERROR_CAN4_RX_BUF_OF);  
00165     C4CMR = 1<<2; //Release CAN data buffer
00166     return;
00167   }
00168 
00169   ++can_rx_frame_count_4; // Count received frame
00170 
00171   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN4;
00172   csr_can_rx_buffer[temp_index].addr            = C4RID;
00173   csr_can_rx_buffer[temp_index].dlc             = (C4RFS>>16)&0xF;
00174   csr_can_rx_buffer[temp_index].rtr             = (C4RFS>>30)&0x1;
00175   csr_can_rx_buffer[temp_index].payload.w.w1    = C4RDA;
00176   csr_can_rx_buffer[temp_index].payload.w.w2    = C4RDB;
00177   
00178   C4CMR = 1<<2; //Release CAN data buffer 
00179    
00180   csr_can_rx_index1 = temp_index;   //update index1
00181 }
00183 
00184 /*
00186 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00187 void csr_can_rx1_isr(void) __irq
00188 {
00189   short int temp_index = csr_can_rx_index1;
00190 
00191   #ifdef DEBUG
00192   if (FIO0PIN & 1<<14)
00193   {
00194     VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00195     VICVectAddr = 0;
00196     return;
00197   }
00198   #endif
00199   
00200   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00201   if (temp_index == csr_can_rx_index2)
00202   {
00203     //Buffer full, new data will be lost; don't advance write index
00204     error_occurred_irq(ERROR_CAN1_RX_BUF_OF);  
00205     C1CMR = 1<<2; //Release CAN data buffer
00206     return;
00207   }
00208   ++can_rx_frame_count_1; // Count received frame
00209 
00210   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN1;
00211   csr_can_rx_buffer[temp_index].addr            = C1RID;
00212   csr_can_rx_buffer[temp_index].dlc             = (C1RFS>>16)&0xF;
00213   csr_can_rx_buffer[temp_index].rtr             = (C1RFS>>30)&0x1;
00214   csr_can_rx_buffer[temp_index].payload.w.w1    = C1RDA;
00215   csr_can_rx_buffer[temp_index].payload.w.w2    = C1RDB;
00216    
00217   C1CMR = 1<<2; //Release CAN data buffer 
00218    
00219   csr_can_rx_index1 = temp_index;   //update index1
00220   VICVectAddr = 0;    // Clear interrupt in VIC.
00221 }
00223 
00225 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00226 void csr_can_rx2_isr(void) __irq
00227 {
00228   short int temp_index = csr_can_rx_index1;
00229 
00230   #ifdef DEBUG
00231   if (FIO0PIN & 1<<14)
00232   {
00233     VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00234     VICVectAddr = 0;
00235     return;
00236   }
00237   #endif
00238 
00239   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00240   if (temp_index == csr_can_rx_index2)
00241   {
00242     //Buffer full, new data will be lost; don't advance write index
00243     error_occurred_irq(ERROR_CAN2_RX_BUF_OF);  
00244     C2CMR = 1<<2; //Release CAN data buffer
00245     return;
00246   }
00247   ++can_rx_frame_count_2; // Count received frame
00248 
00249   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN2;
00250   csr_can_rx_buffer[temp_index].addr            = C2RID;
00251   csr_can_rx_buffer[temp_index].dlc             = (C2RFS>>16)&0xF;
00252   csr_can_rx_buffer[temp_index].rtr             = (C2RFS>>30)&0x1;
00253   csr_can_rx_buffer[temp_index].payload.w.w1    = C2RDA;
00254   csr_can_rx_buffer[temp_index].payload.w.w2    = C2RDB; 
00255 
00256   C2CMR = 1<<2; //Release CAN data buffer 
00257    
00258   csr_can_rx_index1 = temp_index;   //update index1
00259   VICVectAddr = 0;    // Clear interrupt in VIC.
00260 }
00262 
00264 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00265 void csr_can_rx3_isr(void) __irq
00266 {
00267   short int temp_index = csr_can_rx_index1;
00268 
00269   #ifdef DEBUG
00270   if (FIO0PIN & 1<<14)
00271   {
00272     VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00273     VICVectAddr = 0;
00274     return;
00275   }
00276   #endif
00277 
00278   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00279   if (temp_index == csr_can_rx_index2)
00280   {
00281     //Buffer full, new data will be lost; don't advance write index
00282     error_occurred_irq(ERROR_CAN3_RX_BUF_OF);  
00283     C3CMR = 1<<2; //Release CAN data buffer
00284     return;
00285   }
00286 
00287   ++can_rx_frame_count_3; // Count received frame
00288 
00289   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN3;
00290   csr_can_rx_buffer[temp_index].addr            = C3RID;
00291   csr_can_rx_buffer[temp_index].dlc             = (C3RFS>>16)&0xF;
00292   csr_can_rx_buffer[temp_index].rtr             = (C3RFS>>30)&0x1;
00293   csr_can_rx_buffer[temp_index].payload.w.w1    = C3RDA;
00294   csr_can_rx_buffer[temp_index].payload.w.w2    = C1RDB;
00295   
00296   C3CMR = 1<<2; //Release CAN data buffer 
00297    
00298   csr_can_rx_index1 = temp_index;   //update index1
00299   VICVectAddr = 0;    // Clear interrupt in VIC.
00300 }
00302 
00304 //Read CAN rx controller buffer, create CAN frame and push onto receive ring buffer
00305 void csr_can_rx4_isr(void) __irq
00306 {
00307   short int temp_index = csr_can_rx_index1;
00308 
00309   #ifdef DEBUG
00310   if (FIO0PIN & 1<<14)
00311   {
00312     VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00313     VICVectAddr = 0;
00314     return;
00315   }
00316   #endif
00317    
00318   if (++temp_index == CSR_CAN_RX_BUFFER_SIZE) {temp_index = 0;}
00319   if (temp_index == csr_can_rx_index2)
00320   {
00321     //Buffer full, new data will be lost; don't advance write index
00322     error_occurred_irq(ERROR_CAN4_RX_BUF_OF);  
00323     C4CMR = 1<<2; //Release CAN data buffer
00324     return;
00325   }
00326 
00327   ++can_rx_frame_count_4; // Count received frame
00328 
00329   csr_can_rx_buffer[temp_index].chan            = CHAN_CAN4;
00330   csr_can_rx_buffer[temp_index].addr            = C4RID;
00331   csr_can_rx_buffer[temp_index].dlc             = (C4RFS>>16)&0xF;
00332   csr_can_rx_buffer[temp_index].rtr             = (C4RFS>>30)&0x1;
00333   csr_can_rx_buffer[temp_index].payload.w.w1    = C4RDA;
00334   csr_can_rx_buffer[temp_index].payload.w.w2    = C4RDB;
00335   
00336   C4CMR = 1<<2; //Release CAN data buffer 
00337    
00338   csr_can_rx_index1 = temp_index;   //update index1
00339   VICVectAddr = 0;    // Clear interrupt in VIC.
00340 }
00342 */
00343 
00345 //Push one CAN frame onto CAN1 transmit ring buffer
00346 unsigned short int csr_can1_tx_push_frame(CAN_FRAME * frameptr)
00347 {
00348   short int ret = 1, temp_index = csr_can1_tx_index1;
00349   
00350   if (++temp_index == CSR_CAN_TX_BUFFER_SIZE) {temp_index = 0;}
00351 
00352   if (temp_index != csr_can1_tx_index2) 
00353   {
00354     //Push new frame onto buffer
00355     csr_can1_tx_buffer[csr_can1_tx_index1] = *frameptr;
00356     csr_can1_tx_index1 = temp_index;   //update index1
00357     ret = 0; //Frame successfully pushed onto buffer
00358   }
00359    
00360 // uncomment the following two lines for use with isr
00361  // VICSoftInt = 1<<20;   //Force CAN1 TX interrupt
00362  // VICIntEnable = 1<<20; //Enable CAN1 TX interrupts
00363   
00364   return ret; // 0 = successful push, 1 = buffer full
00365 }
00366 
00367 /*
00369 void csr_can1_tx_isr(void) __irq
00370 {
00371   #ifdef DEBUG
00372     if (FIO0PIN & 1<<14)
00373     {
00374       VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00375       VICVectAddr = 0;
00376       return;
00377     }
00378   #endif
00379   
00380   while (csr_can1_tx_index2 != csr_can1_tx_index1)
00381   {
00382     if (C1SR & (1<<2)) // buffer 1 is available
00383     {   
00384       C1TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00385       C1TID1 = csr_can1_tx_buffer[csr_can1_tx_index2].addr;   //get CAN_ID
00386       C1TDA1 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w1;   //load first data word
00387       C1TDB1 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w2;   //load second data word 
00388       C1CMR = (1<<0) | (1<<5);     // Select buffer 1, request transmission
00389       if (++csr_can1_tx_index2 == CSR_CAN_TX_BUFFER_SIZE) {csr_can1_tx_index2 = 0;}
00390 
00391       //Move to next read index location
00392       if (csr_can1_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00393       {
00394         csr_can1_tx_index2 = 0;
00395       }
00396       else
00397       {
00398         ++csr_can1_tx_index2;
00399       }
00400 
00401       can_tx_frame_count_1++;
00402     //  b10a_can_packet_count(1);
00403     }
00404     else if (C1SR & (1<<10)) // buffer 2 is available
00405     {
00406       C1TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00407       C1TID2 = csr_can1_tx_buffer[csr_can1_tx_index2].addr;   //get CAN_ID
00408       C1TDA2 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w1;   //load first data word
00409       C1TDB2 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w2;   //load second data word 
00410       C1CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00411 
00412       //Move to next read index location
00413       if (csr_can1_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00414       {
00415         csr_can1_tx_index2 = 0;
00416       }
00417       else
00418       {
00419         ++csr_can1_tx_index2;
00420       }
00421 
00422 
00423       can_tx_frame_count_1++;
00424      // b10a_can_packet_count(1);
00425     }
00426     else
00427     {
00428       break;   //all available buffers full
00429     } 
00430   }
00431   
00432   if (csr_can1_tx_index2 == csr_can1_tx_index1)
00433   {
00434 //   C1IER = (C1IER & (~(1<<1))) & 0x7FF; // clear TIE1 (Transmit Interrupt Enable 1) and mask reserved bits
00435     VICIntEnClr = 1<<20; //Disable CAN1 TX interrupts
00436   }
00437     
00438   VICSoftIntClr = 1<<20;  //Clear any CAN1 TX software interrupt
00439   VICVectAddr = 0;    // Clear interrupt in VIC.
00440 }
00442 */
00444 void csr_can1_tx(void)
00445 {
00446   while (csr_can1_tx_index2 != csr_can1_tx_index1)
00447   {
00448     if (C1SR & (1<<2)) // buffer 1 is available
00449     {   
00450       C1TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00451       C1TID1 = csr_can1_tx_buffer[csr_can1_tx_index2].addr;   //get CAN_ID
00452       C1TDA1 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w1;   //load first data word
00453       C1TDB1 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w2;   //load second data word 
00454       C1CMR = (1<<0) | (1<<5);     // Select buffer 1, request transmission
00455 
00456       //Move to next read index location
00457       if (csr_can1_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00458       {
00459         csr_can1_tx_index2 = 0;
00460       }
00461       else
00462       {
00463         ++csr_can1_tx_index2;
00464       }
00465 
00466       can_tx_frame_count_1++;
00467     //  b10a_can_packet_count(1);
00468     }
00469     else if (C1SR & (1<<10)) // buffer 2 is available
00470     {
00471       C1TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00472       C1TID2 = csr_can1_tx_buffer[csr_can1_tx_index2].addr;   //get CAN_ID
00473       C1TDA2 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w1;   //load first data word
00474       C1TDB2 = csr_can1_tx_buffer[csr_can1_tx_index2].payload.w.w2;   //load second data word 
00475       C1CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00476 
00477       //Move to next read index location
00478       if (csr_can1_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00479       {
00480         csr_can1_tx_index2 = 0;
00481       }
00482       else
00483       {
00484         ++csr_can1_tx_index2;
00485       }
00486 
00487 
00488       can_tx_frame_count_1++;
00489      // b10a_can_packet_count(1);
00490     }
00491     else
00492     {
00493       return;   //all available buffers full
00494     } 
00495   }
00496 }
00498 
00500 //Push one CAN frame onto CAN2 transmit ring buffer
00501 unsigned short int csr_can2_tx_push_frame(CAN_FRAME * frameptr)
00502 {
00503   short int ret = 1, temp_index = csr_can2_tx_index1;
00504   
00505   if (++temp_index == CSR_CAN_TX_BUFFER_SIZE) {temp_index = 0;}
00506 
00507   if (temp_index != csr_can2_tx_index2) 
00508   {
00509     //Push new frame onto buffer
00510     csr_can2_tx_buffer[csr_can2_tx_index1] = *frameptr;
00511     csr_can2_tx_index1 = temp_index;   //update index1
00512     ret = 0; //Frame successfully pushed onto buffer
00513   }
00514  
00515 // uncomment the following two lines for use with isr  
00516   //VICSoftInt = 1<<21;   //Force CAN2 TX interrupt
00517   //VICIntEnable = 1<<21; //Enable CAN2 TX interrupts
00518   
00519   return ret; // 0 = successful push, 1 = buffer full
00520 }
00521 
00523 /*
00524 void csr_can2_tx_isr(void) __irq
00525 {
00526  #ifdef DEBUG
00527     if (FIO0PIN & 1<<14)
00528     {
00529       VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00530       VICVectAddr = 0;
00531       return;
00532     }
00533   #endif
00534   
00535   while (csr_can2_tx_index2 != csr_can2_tx_index1)
00536   {
00537     if (C2SR & (1<<2)) // buffer 1 is available
00538     {   
00539       C2TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00540       C2TID1 = csr_can2_tx_buffer[csr_can2_tx_index2].addr;   //get CAN_ID
00541       C2TDA1 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w1;   //load first data word
00542       C2TDB1 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w2;   //load second data word 
00543       C2CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00544       can_tx_frame_count_2++;
00545 
00546       //Move to next read index location
00547       if (csr_can2_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00548       {
00549         csr_can2_tx_index2 = 0;
00550       }
00551       else
00552       {
00553         ++csr_can2_tx_index2;
00554       }
00555     }
00556     else if (C2SR & (1<<10)) // buffer 2 is available
00557     {
00558       C2TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00559       C2TID2 = csr_can2_tx_buffer[csr_can2_tx_index2].addr;   //get CAN_ID
00560       C2TDA2 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w1;   //load first data word
00561       C2TDB2 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w2;   //load second data word 
00562       C2CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00563       can_tx_frame_count_2++;
00564 
00565       //Move to next read index location
00566       if (csr_can2_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00567       {
00568         csr_can2_tx_index2 = 0;
00569       }
00570       else
00571       {
00572         ++csr_can2_tx_index2;
00573       }
00574     }
00575     else
00576     {
00577       break;   //all available buffers full
00578     } 
00579   }
00580   if (csr_can2_tx_index2 == csr_can2_tx_index1)
00581   {
00582     VICIntEnClr = 1<<21; //Disable CAN2 TX interrupts
00583   }
00584   
00585   VICSoftIntClr = 1<<21;  //Clear any CAN2 TX software interrupt
00586   VICVectAddr = 0;    // Clear interrupt in VIC.
00587 }
00589 */
00591 void csr_can2_tx(void)
00592 {  
00593   while (csr_can2_tx_index2 != csr_can2_tx_index1)
00594   {
00595     if (C2SR & (1<<2)) // buffer 1 is available
00596     {   
00597       C2TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00598       C2TID1 = csr_can2_tx_buffer[csr_can2_tx_index2].addr;   //get CAN_ID
00599       C2TDA1 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w1;   //load first data word
00600       C2TDB1 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w2;   //load second data word 
00601       C2CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00602       can_tx_frame_count_2++;
00603 
00604       //Move to next read index location
00605       if (csr_can2_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00606       {
00607         csr_can2_tx_index2 = 0;
00608       }
00609       else
00610       {
00611         ++csr_can2_tx_index2;
00612       }
00613     }
00614     else if (C2SR & (1<<10)) // buffer 2 is available
00615     {
00616       C2TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00617       C2TID2 = csr_can2_tx_buffer[csr_can2_tx_index2].addr;   //get CAN_ID
00618       C2TDA2 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w1;   //load first data word
00619       C2TDB2 = csr_can2_tx_buffer[csr_can2_tx_index2].payload.w.w2;   //load second data word 
00620       C2CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00621       can_tx_frame_count_2++;
00622 
00623       //Move to next read index location
00624       if (csr_can2_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00625       {
00626         csr_can2_tx_index2 = 0;
00627       }
00628       else
00629       {
00630         ++csr_can2_tx_index2;
00631       }
00632     }
00633     else
00634     {
00635       return;   //all available buffers full
00636     } 
00637   }
00638 }
00640 
00641 
00643 //Push one CAN frame onto CAN3 transmit ring buffer
00644 unsigned short int csr_can3_tx_push_frame(CAN_FRAME * frameptr)
00645 {
00646   short int ret = 1, temp_index = csr_can3_tx_index1;
00647   
00648   if (++temp_index == CSR_CAN_TX_BUFFER_SIZE) {temp_index = 0;}
00649 
00650   if (temp_index != csr_can3_tx_index2) 
00651   {
00652     //Push new frame onto buffer
00653     csr_can3_tx_buffer[csr_can3_tx_index1] = *frameptr;
00654     csr_can3_tx_index1 = temp_index;   //update index1
00655     ret = 0; //Frame successfully pushed onto buffer
00656   }
00657   
00658  // uncomment the following two lines for use with isr
00659  // VICSoftInt = 1<<22;   //Force CAN3 TX interrupt
00660   //VICIntEnable = 1<<22; //Enable CAN3 TX interrupts
00661   
00662   return ret; // 0 = successful push, 1 = buffer full
00663 }
00664 
00666 /*
00667 void csr_can3_tx_isr(void) __irq
00668 {
00669  #ifdef DEBUG
00670     if (FIO0PIN & 1<<14)
00671     {
00672       VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00673       VICVectAddr = 0;
00674       return;
00675     }
00676   #endif
00677 
00678   while (csr_can3_tx_index2 != csr_can3_tx_index1)
00679   {
00680     if (C3SR & (1<<2)) // buffer 1 is available
00681     {   
00682       C3TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00683       C3TID1 = csr_can3_tx_buffer[csr_can3_tx_index2].addr;   //get CAN_ID
00684       C3TDA1 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w1;   //load first data word
00685       C3TDB1 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w2;   //load second data word 
00686       C3CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00687       can_tx_frame_count_3++;
00688  
00689       //Move to next read index location
00690       if (csr_can3_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00691       {
00692         csr_can3_tx_index2 = 0;
00693       }
00694       else
00695       {
00696         ++csr_can3_tx_index2;
00697       }
00698     }
00699     else if (C3SR & (1<<10)) // buffer 2 is available
00700     {
00701       C3TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00702       C3TID2 = csr_can3_tx_buffer[csr_can3_tx_index2].addr;   //get CAN_ID
00703       C3TDA2 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w1;   //load first data word
00704       C3TDB2 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w2;   //load second data word 
00705       C3CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00706       can_tx_frame_count_3++;
00707 
00708       //Move to next read index location
00709       if (csr_can3_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00710       {
00711         csr_can3_tx_index2 = 0;
00712       }
00713       else
00714       {
00715         ++csr_can3_tx_index2;
00716       }
00717     }
00718     else
00719     {
00720       break;   //all available buffers full
00721     } 
00722   }
00723   if (csr_can3_tx_index2 == csr_can3_tx_index1)
00724   {
00725     VICIntEnClr = 1<<22; //Disable CAN3 TX interrupts
00726   }
00727   
00728   VICSoftIntClr = 1<<22;  //Clear any CAN3 TX software interrupt
00729   VICVectAddr = 0;    // Clear interrupt in VIC.
00730 }
00732 */
00734 void csr_can3_tx(void)
00735 {
00736   while (csr_can3_tx_index2 != csr_can3_tx_index1)
00737   {
00738     if (C3SR & (1<<2)) // buffer 1 is available
00739     {   
00740       C3TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00741       C3TID1 = csr_can3_tx_buffer[csr_can3_tx_index2].addr;   //get CAN_ID
00742       C3TDA1 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w1;   //load first data word
00743       C3TDB1 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w2;   //load second data word 
00744       C3CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00745       can_tx_frame_count_3++;
00746  
00747       //Move to next read index location
00748       if (csr_can3_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00749       {
00750         csr_can3_tx_index2 = 0;
00751       }
00752       else
00753       {
00754         ++csr_can3_tx_index2;
00755       }
00756     }
00757     else if (C3SR & (1<<10)) // buffer 2 is available
00758     {
00759       C3TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00760       C3TID2 = csr_can3_tx_buffer[csr_can3_tx_index2].addr;   //get CAN_ID
00761       C3TDA2 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w1;   //load first data word
00762       C3TDB2 = csr_can3_tx_buffer[csr_can3_tx_index2].payload.w.w2;   //load second data word 
00763       C3CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00764       can_tx_frame_count_3++;
00765 
00766       //Move to next read index location
00767       if (csr_can3_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00768       {
00769         csr_can3_tx_index2 = 0;
00770       }
00771       else
00772       {
00773         ++csr_can3_tx_index2;
00774       }
00775     }
00776     else
00777     {
00778       return;   //all available buffers full
00779     } 
00780   }
00781 }
00783 
00784 
00786 //Push one CAN frame onto CAN4 transmit ring buffer
00787 unsigned short int csr_can4_tx_push_frame(CAN_FRAME * frameptr)
00788 {
00789   short int ret = 1, temp_index = csr_can4_tx_index1;
00790   
00791   if (++temp_index == CSR_CAN_TX_BUFFER_SIZE) {temp_index = 0;}
00792 
00793   if (temp_index != csr_can4_tx_index2) 
00794   {
00795     //Push new frame onto buffer
00796     csr_can4_tx_buffer[csr_can4_tx_index1] = *frameptr;
00797     csr_can4_tx_index1 = temp_index;   //update index1
00798     ret = 0; //Frame successfully pushed onto buffer
00799   }
00800   
00801 // uncomment the following two lines for use with isr
00802   //VICSoftInt = 1<<23;   //Force CAN4 TX interrupt
00803   //VICIntEnable = 1<<23; //Enable CAN4 TX interrupts
00804   
00805   return ret; // 0 = successful push, 1 = buffer full
00806 }
00807 
00809 /*
00810 void csr_can4_tx_isr(void) __irq
00811 {
00812  #ifdef DEBUG
00813     if (FIO0PIN & 1<<14)
00814     {
00815       VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
00816       VICVectAddr = 0;
00817       return;
00818     }
00819   #endif
00820 
00821   while (csr_can4_tx_index2 != csr_can4_tx_index1)
00822   {
00823     if (C4SR & (1<<2)) // buffer 1 is available
00824     {   
00825       C4TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00826       C4TID1 = csr_can4_tx_buffer[csr_can4_tx_index2].addr;   //get CAN_ID
00827       C4TDA1 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w1;   //load first data word
00828       C4TDB1 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w2;   //load second data word 
00829       C4CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00830       can_tx_frame_count_4++;
00831  
00832       //Move to next read index location
00833       if (csr_can4_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00834       {
00835         csr_can4_tx_index2 = 0;
00836       }
00837       else
00838       {
00839         ++csr_can4_tx_index2;
00840       }
00841     }
00842     else if (C4SR & (1<<10)) // buffer 2 is available
00843     {
00844       C4TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00845       C4TID2 = csr_can4_tx_buffer[csr_can4_tx_index2].addr;   //get CAN_ID
00846       C4TDA2 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w1;   //load first data word
00847       C4TDB2 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w2;   //load second data word 
00848       C4CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00849       can_tx_frame_count_4++;
00850 
00851       //Move to next read index location
00852       if (csr_can4_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00853       {
00854         csr_can4_tx_index2 = 0;
00855       }
00856       else
00857       {
00858         ++csr_can4_tx_index2;
00859       }
00860     }
00861     else
00862     {
00863       break;   //all available buffers full
00864     } 
00865   }
00866   if (csr_can4_tx_index2 == csr_can4_tx_index1)
00867   {
00868     VICIntEnClr = 1<<23; //Disable CAN4 TX interrupts
00869   }
00870   
00871   VICSoftIntClr = 1<<23;  //Clear any CAN4 TX software interrupt
00872   VICVectAddr = 0;    // Clear interrupt in VIC.
00873 }
00875 */
00877 void csr_can4_tx(void)
00878 {
00879   while (csr_can4_tx_index2 != csr_can4_tx_index1)
00880   {
00881     if (C4SR & (1<<2)) // buffer 1 is available
00882     {   
00883       C4TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00884       C4TID1 = csr_can4_tx_buffer[csr_can4_tx_index2].addr;   //get CAN_ID
00885       C4TDA1 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w1;   //load first data word
00886       C4TDB1 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w2;   //load second data word 
00887       C4CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00888       can_tx_frame_count_4++;
00889  
00890       //Move to next read index location
00891       if (csr_can4_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00892       {
00893         csr_can4_tx_index2 = 0;
00894       }
00895       else
00896       {
00897         ++csr_can4_tx_index2;
00898       }
00899     }
00900     else if (C4SR & (1<<10)) // buffer 2 is available
00901     {
00902       C4TFI2 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00903       C4TID2 = csr_can4_tx_buffer[csr_can4_tx_index2].addr;   //get CAN_ID
00904       C4TDA2 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w1;   //load first data word
00905       C4TDB2 = csr_can4_tx_buffer[csr_can4_tx_index2].payload.w.w2;   //load second data word 
00906       C4CMR = (1<<0) | (1<<6);     // select buffer 2, request transmission
00907       can_tx_frame_count_4++;
00908 
00909       //Move to next read index location
00910       if (csr_can4_tx_index2 >= CSR_CAN_TX_BUFFER_SIZE - 1)
00911       {
00912         csr_can4_tx_index2 = 0;
00913       }
00914       else
00915       {
00916         ++csr_can4_tx_index2;
00917       }
00918     }
00919     else
00920     {
00921       return;   //all available buffers full
00922     } 
00923   }
00924 }
00925 /*
00927 
00928 // **** TEST CODE **** send dummy data, no buffers involved
00930 void csr_can1_tx_test(void)
00931 {
00932     if (C1SR & (1<<2)) // buffer 1 is available
00933     {   
00934       C1TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00935       C1TID1 = 600;   //get CAN_ID
00936       C1TDA1 = 0xAAAAAAAA;   //load first data word
00937       C1TDB1 = 0xBBBBBBBB;   //load second data word  
00938       C1CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00939       can_tx_frame_count_1++;
00940     }
00941     if (C1SR & (1<<10)) // buffer 2 is available
00942     {
00943      C1TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00944       C1TID1 = 601;   //get CAN_ID
00945       C1TDA1 = 0xAAAAAAAA;   //load first data word
00946       C1TDB1 = 0xBBBBBBBB;   //load second data word  
00947       C1CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00948       can_tx_frame_count_1++;
00949     }
00950 }
00952 
00953 // **** TEST CODE **** send dummy data, no buffers involved
00955 void csr_can2_tx_test(void)
00956 {
00957     if (C2SR & (1<<2)) // buffer 1 is available
00958     {   
00959       C2TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00960       C2TID1 = 602;   //get CAN_ID
00961       C2TDA1 = 0xAAAAAAAA;   //load first data word
00962       C2TDB1 = 0xBBBBBBBB;   //load second data word  
00963       C2CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00964       can_tx_frame_count_2++;
00965     }
00966     if (C2SR & (1<<10)) // buffer 2 is available
00967     {
00968      C2TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00969       C2TID1 = 603;   //get CAN_ID
00970       C2TDA1 = 0xAAAAAAAA;   //load first data word
00971       C2TDB1 = 0xBBBBBBBB;   //load second data word  
00972       C2CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00973       can_tx_frame_count_2++;
00974     }
00975 }
00977 
00978 // **** TEST CODE **** send dummy data, no buffers involved
00980 void csr_can3_tx_test(void)
00981 {
00982     if (C3SR & (1<<2)) // buffer 1 is available
00983     {   
00984       C3TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00985       C3TID1 = 604;   //get CAN_ID
00986       C3TDA1 = 0xAAAAAAAA;   //load first data word
00987       C3TDB1 = 0xBBBBBBBB;   //load second data word  
00988       C3CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00989       can_tx_frame_count_3++;
00990     }
00991     if (C3SR & (1<<10)) // buffer 2 is available
00992     {
00993      C3TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
00994       C3TID1 = 605;   //get CAN_ID
00995       C3TDA1 = 0xAAAAAAAA;   //load first data word
00996       C3TDB1 = 0xBBBBBBBB;   //load second data word  
00997       C3CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
00998       can_tx_frame_count_3++;
00999     }
01000 }
01002 
01003 // **** TEST CODE **** send dummy data, no buffers involved
01005 void csr_can4_tx_test(void)
01006 {
01007     if (C4SR & (1<<2)) // buffer 1 is available
01008     {   
01009       C4TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
01010       C4TID1 = 605;   //get CAN_ID
01011       C4TDA1 = 0xAAAAAAAA;   //load first data word
01012       C4TDB1 = 0xBBBBBBBB;   //load second data word  
01013       C4CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
01014       can_tx_frame_count_4++;
01015     }
01016     if (C4SR & (1<<10)) // buffer 2 is available
01017     {
01018      C4TFI1 = 1<<19;  //Data length 8, FF = 0, RTR = 0, PRIO = 0
01019       C4TID1 = 606;   //get CAN_ID
01020       C4TDA1 = 0xAAAAAAAA;   //load first data word
01021       C4TDB1 = 0xBBBBBBBB;   //load second data word  
01022       C4CMR = (1<<0) | (1<<5);     // select buffer 1, request transmission
01023       can_tx_frame_count_4++;
01024     }
01025 }
01027 */
01028 
01029 unsigned short can_get_error_1(CAN_FRAME * frame)
01030 {
01031   frame->payload.w.w1 = can_error_1;
01032   can_error_1 = 0;     //Reset error
01033   frame->payload.w.w2 = 0;
01034   return 0;
01035 }
01036 
01037 unsigned short can_get_error_2(CAN_FRAME * frame)
01038 {
01039   frame->payload.w.w1 = can_error_2;
01040   can_error_2 = 0;     //Reset error
01041   frame->payload.w.w2 = 0;
01042   return 0;
01043 }
01044 
01045 unsigned short can_get_error_3(CAN_FRAME * frame)
01046 {
01047   frame->payload.w.w1 = can_error_3;
01048   can_error_3 = 0;     //Reset error
01049   frame->payload.w.w2 = 0;
01050   return 0;
01051 }
01052 
01053 unsigned short can_get_error_4(CAN_FRAME * frame)
01054 {
01055   frame->payload.w.w1 = can_error_4;
01056   can_error_4 = 0;     //Reset error
01057   frame->payload.w.w2 = 0;
01058   return 0;
01059 }
01060 
01061 
01062  void can_error_isr(void) __irq
01063 {
01064  volatile int can_status1; //save state of capture register
01065  volatile int can_status2; //save state of capture register
01066  volatile int can_status3; //save state of capture register
01067  volatile int can_status4; //save state of capture register
01068  
01069  volatile unsigned long can_acc_filter_error;   //save location of error in AF lookup table
01070   
01071   #ifdef DEBUG
01072     if (FIO0PIN & 1<<14)
01073     {
01074       VICIntEnClr = 0xFFFFFFFF; //Disable all interrupts before debugging
01075       VICVectAddr = 0;
01076       return;
01077     }
01078   #endif
01079 
01080   if (LUTerr & (1<<0))
01081   {
01082     can_acc_filter_error = LUTerrAd;  // Address in look-up table RAM (AF) at which error was encountered
01083                                       // Reading this register clears LUTerr error flag
01084     error_occurred_irq(ERROR_CAN_ACC_FILTER);  // Acceptance filter error - most likely a table error
01085   }
01086 
01087 #ifdef USE_CAN1
01088   if (C1GSR & (1<<7))
01089   { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
01090     C1MOD = 0; //restart the can bus
01091     error_occurred_irq(ERROR_CAN1_TX_BUSOFF);  // Transmit errors leading to bus off error state
01092     can_error_1 = ERROR_CAN1_TX_BUSOFF;
01093     //can_tx_send_next_frame(CHAN_CAN1); //start the transmissions again
01094     //VICSoftInt = 1<<20;   //Force CAN1 TX interrupt     // **** TEST CODE ****
01095   }
01096   can_status1 = C1ICR; //save state of capture register
01097     if (can_status1 & ((1<<2)|(1<<3)|(1<<5)|(1<<7)))
01098   {
01099     if (can_status1 & (1<<2))
01100     {
01101       can_error_1 = ERROR_CAN1_ERR_WARN;
01102       error_occurred_irq(ERROR_CAN1_ERR_WARN);  // Shows change in error or bus status bits in either direction
01103     }
01104     if (can_status1 & (1<<3))
01105     {
01106       can_error_1 = ERROR_CAN1_DATA_OVRN;
01107       error_occurred_irq(ERROR_CAN1_DATA_OVRN);  // Receive data overrun on CAN1 - receive buffer not read before
01108                                                     // arrival of next received frame, data lost
01109     }
01110     if (can_status1 & (1<<5))
01111     {
01112       can_error_1 = ERROR_CAN1_ERR_PASS;
01113       error_occurred_irq(ERROR_CAN1_ERR_PASS);  // Shows change in active or passive error status in either direction
01114     }
01115     if (can_status1 & (1<<7))
01116     {
01117       if (can_status1 & (1<<21))
01118       {
01119         can_error_1 = ERROR_CAN1_BUS_RX;
01120         error_occurred_irq(ERROR_CAN1_BUS_RX);  // CAN1 has detected an rx bus error. Details of the error require reading
01121                                                   // the other bits in can_status1. For now that has to be done in the debugger,
01122                                                   // including all the possiblities in the ERROR_IDs would be cumbersome.
01123                                                   // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
01124       }                                           // if we wanted.
01125       else
01126       {
01127          can_error_1 = ERROR_CAN1_BUS_TX;
01128          error_occurred_irq(ERROR_CAN1_BUS_TX);
01129       }
01130     }
01131   } 
01132 #endif
01133 
01134 #ifdef USE_CAN2
01135   if (C2GSR & (1<<7))
01136   { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
01137     C2MOD = 0; //restart the can bus
01138     error_occurred_irq(ERROR_CAN2_TX_BUSOFF);  // Transmit errors leading to bus off error state
01139     can_error_2 = ERROR_CAN2_TX_BUSOFF;
01140    // can_tx_send_next_frame(CHAN_CAN2); //start the transmissions again
01141     //VICSoftInt = 1<<21;   //Force CAN2 TX interrupt     // **** TEST CODE ****
01142   }
01143   can_status2 = C2ICR; //save state of capture register
01144   if (can_status2 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
01145   {
01146     if (can_status2 & (1<<2))
01147     {
01148       can_error_2 = ERROR_CAN2_ERR_WARN;
01149       error_occurred_irq(ERROR_CAN2_ERR_WARN);  // Shows change in error or bus status bits in either direction
01150     }
01151     if (can_status2 & (1<<3))
01152     {
01153       can_error_2 = ERROR_CAN2_DATA_OVRN;
01154       error_occurred_irq(ERROR_CAN2_DATA_OVRN);  // Receive data overrun on CAN2 - receive buffer not read before
01155                                                     // arrival of next received frame, data lost
01156     }
01157     if (can_status2 & (1<<5))
01158     {
01159       can_error_2 = ERROR_CAN2_ERR_PASS;
01160       error_occurred_irq(ERROR_CAN2_ERR_PASS);  // Shows change in active or passive error status in either direction
01161     }
01162     if (can_status2 & (1<<7))
01163     {
01164       if (can_status2 & (1<<21))
01165       {
01166         can_error_2 = ERROR_CAN2_BUS_RX;
01167         error_occurred_irq(ERROR_CAN2_BUS_RX);  // CAN2 has detected an rx bus error. Details of the error require reading
01168                                                   // the other bits in can_status1. For now that has to be done in the debugger,
01169                                                   // including all the possiblities in the ERROR_IDs would be cumbersome.
01170                                                   // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
01171                                                   // if we wanted.
01172       }
01173       else
01174       {
01175         can_error_2 = ERROR_CAN2_BUS_TX;
01176          error_occurred_irq(ERROR_CAN2_BUS_TX);
01177       }
01178     }
01179   }
01180 #endif
01181 
01182 #ifdef USE_CAN3
01183   if (C3GSR & (1<<7))
01184   { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
01185     C3MOD = 0; //restart the can bus
01186     error_occurred_irq(ERROR_CAN3_TX_BUSOFF);  // Transmit errors leading to bus off error state
01187     can_error_3 = ERROR_CAN3_TX_BUSOFF;
01188     //can_tx_send_next_frame(CHAN_CAN3); //start the transmissions again
01189     //VICSoftInt = 1<<22;   //Force CAN3 TX interrupt     // **** TEST CODE ****
01190   } 
01191   can_status3 = C3ICR; //save state of capture register
01192   if (can_status3 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
01193   {
01194     if (can_status3 & (1<<2))
01195     {
01196       can_error_3 = ERROR_CAN3_ERR_WARN;
01197       error_occurred_irq(ERROR_CAN3_ERR_WARN);  // Shows change in error or bus status bits in either direction
01198     }
01199     if (can_status3 & (1<<3))
01200     {
01201       can_error_3 = ERROR_CAN3_DATA_OVRN;
01202       error_occurred_irq(ERROR_CAN3_DATA_OVRN);  // Receive data overrun on CAN3 - receive buffer not read before
01203                                                     // arrival of next received frame, data lost
01204     }
01205     if (can_status3 & (1<<5))
01206     {
01207       can_error_3 = ERROR_CAN3_ERR_PASS;
01208       error_occurred_irq(ERROR_CAN3_ERR_PASS);  // Shows change in active or passive error status in either direction
01209     }
01210     if (can_status3 & (1<<7))
01211     {
01212       if (can_status3 & (1<<21))
01213       {
01214         can_error_3 = ERROR_CAN3_BUS_RX;
01215         error_occurred_irq(ERROR_CAN3_BUS_RX);  // CAN3 has detected an rx bus error. Details of the error require reading
01216                                                   // the other bits in can_status1. For now that has to be done in the debugger,
01217                                                   // including all the possiblities in the ERROR_IDs would be cumbersome.
01218                                                   // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
01219                                                   // if we wanted.
01220       }
01221       else
01222       {
01223          can_error_3 = ERROR_CAN3_BUS_TX;
01224          error_occurred_irq(ERROR_CAN3_BUS_TX);
01225       }
01226     }
01227   }
01228 #endif
01229 
01230 #ifdef USE_CAN4
01231   if (C4GSR & (1<<7))
01232   { //Bus-off due to too many transmit errors. Probably because someone flashed a board somewhere...
01233     C4MOD = 0; //restart the can bus
01234     error_occurred_irq(ERROR_CAN4_TX_BUSOFF);  // Transmit errors leading to bus off error state
01235     can_error_4 = ERROR_CAN4_TX_BUSOFF;
01236    // can_tx_send_next_frame(CHAN_CAN4); //start the transmissions again
01237    // VICSoftInt = 1<<23;   //Force CAN4 TX interrupt     // **** TEST CODE ****
01238   }
01239   can_status4 = C4ICR; //save state of capture register 
01240   
01241   if (can_status4 & (((1<<2)|(1<<3)|(1<<5)|(1<<7))&0x7FF))
01242   {
01243     if (can_status4 & (1<<2))
01244     {
01245       can_error_4 = ERROR_CAN4_ERR_WARN;
01246       error_occurred_irq(ERROR_CAN4_ERR_WARN);  // Shows change in error or bus status bits in either direction
01247     }
01248     if (can_status4 & (1<<3))
01249     {
01250       can_error_4 = ERROR_CAN4_DATA_OVRN;
01251       error_occurred_irq(ERROR_CAN4_DATA_OVRN);  // Receive data overrun on CAN4 - receive buffer not read before
01252                                                     // arrival of next received frame, data lost
01253     }
01254     if (can_status4 & (1<<5))
01255     {
01256       can_error_4 = ERROR_CAN4_ERR_PASS;
01257       error_occurred_irq(ERROR_CAN4_ERR_PASS);  // Shows change in active or passive error status in either direction
01258     }
01259     if (can_status4 & (1<<7))
01260     {
01261       if (can_status4 & (1<<21))
01262       {
01263         can_error_4 = ERROR_CAN4_BUS_RX;
01264         error_occurred_irq(ERROR_CAN4_BUS_RX);  // CAN4 has detected an rx bus error. Details of the error require reading
01265                                                   // the other bits in can_status1. For now that has to be done in the debugger,
01266                                                   // including all the possiblities in the ERROR_IDs would be cumbersome.
01267                                                   // But we could make a non-error CAN_FRAME dedicated to the CAN error status register,
01268                                                   // if we wanted.
01269       }
01270       else
01271       {
01272         can_error_4 = ERROR_CAN4_BUS_TX;
01273         error_occurred_irq(ERROR_CAN4_BUS_TX);
01274       }
01275     }
01276   }
01277  #endif
01278   //To do? Put software interrupt force bits for all tx channels here? What about 2-channel MCUs vs. 4-channel?
01279 
01280   VICVectAddr = 0;
01281 }
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